1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method of filling intervals and fabricating shallow trench isolation structures.
2. Description of the Related Art
In semiconductor manufacturing, devices are connected through conductive lines. In addition, a via plug is used to connect an integrated circuit device to a conductive line or the conductive lines in two different layers. To prevent a short circuit due to a direct contact, a dielectric layer or inter-metal dielectric (IMD) layer is interposed between a conductive line and a semiconductor device or between an upper conductive line and a lower conductive line (except for the place with via plugs).
However, with an increase in the level of integration of semiconductor devices, size of each device shrinks so that the aspect ratio of the intervals between conductive lines increases significantly. Thus, filling the intervals between conductive lines with a dielectric material has become increasingly difficult. Furthermore, as the distance of separation between conductive lines is reduced, resistivity of the conductive line and the size of parasitic capacitance are critical factors in determining the speed of the device. To provide a sufficiently fast operating speed for a shrunken semiconductor device, the dielectric material isolating the conductive lines must meet some property requirements. The dielectric material not only must fill the intervals between the conductive lines completely, but also must have superior planarizing capacity. In addition, the dielectric material must also prevent the percolation of moisture and have a low dielectric constant to minimize parasitic capacitance between neighboring conductive lines.
Typically, a high density plasma chemical vapor deposition (HDPCVD) process produces a compact dielectric layer with both moisture blocking capacity and planarity superior to another dielectric layer formed by other chemical vapor deposition process. Hence, the HDPCVD process is the principal method of depositing oxide material to fill intervals. However, as the level of integration of integrated circuit devices continues to increase, the aspect ratio of the interval between neighboring conductive lines also increases correspondingly. Under such circumstance, even the HDPCVD process can hardly fill the intervals completely so that voids are frequently formed within the dielectric layer leading to a drop in the overall production yield.
Aside from an incomplete filling of intervals by the dielectric material layer, the same problem occurs in the fabrication of shallow trench isolation structures as well. As the level of integration increases, each active region must occupy a smaller area. Hence, the shallow trench isolation structures between the active regions must also be reduced. In other words, the aspect ratio of the trench for forming the shallow trench isolation structure is reduced so much that even a HDPCVD process can hardly fill the trench with dielectric material. Since the yield in subsequent processes is likely to be affected by any voids inside the dielectric layer, researchers are constantly on the lookout for a simple method for completely filling the intervals (or trenches) with dielectric material.